As an operational amplifier that enables wide input and output ranges, the operational amplifier with the wide input and output ranges as shown in FIG. 17 is disclosed in JP Patent Kokai Publication JP-A-5-63464. The operational amplifier in FIG. 17 is comprised of a differential circuit 910 and an output stage 950. In the differential circuit 910, a current mirror circuit composed by PMOS transistors (912, 913) (referred to as a “PMOS current mirror circuit”) is connected as a load circuit to outputs of a differential pair of NMOS transistors (915, 916) (also referred to an “NMOS differential pair), driven by a current source 917. Further, input terminals of two pairs of current mirror circuits composed by NMOS transistors (referred to as “NMOS current mirror circuits”) are respectively connected to outputs of a differential pair of PMOS transistors (925, 926) (also referred to as a “PMOS differential pair”), driven by a current source 927. That is, an input terminal of a first NMOS current mirror circuit (921, 922) (a drain of the transistor 922) is connected to the drain of the PMOS transistor 925 constituting the output terminal of the PMOS differential pair (925, 926), and the input terminal of a second NMOS current mirror circuit (923, 924) (the drain of the transistor 923) is connected to the drain of the PMOS transistor 926 constituting the output terminal of the PMOS differential pair (925, 926).
The drain of the transistor 921, which constitutes an output terminal of the first NMOS current mirror circuit (921, 922) is connected to a connecting point between the drain of the transistor 915 constituting the output terminal of the NMOS differential pair (915, 916) and the drain of the transistor 912 constituting the output terminal of the PMOS current mirror circuit (912, 913). The drain of the transistor 924 constituting the output terminal of the second NMOS current mirror circuit (923, 924) is connected to a connecting point between the drain of the transistor 916 constituting the output terminal of the NMOS differential pair (915, 916) and the drain of the transistor 913 constituting the input terminal of the PMOS current mirror circuit (912, 913).
A gate of the transistor 915 of the NMOS differential pair and the gate of the transistor 926 of the PMOS differential pair are connected to a common connecting point, to which an input terminal voltage Vin is supplied.
The gate of the transistor 916 of the NMOS differential pair and the gate of the transistor 925 of the PMOS differential pair are connected to a common connecting point, to which an output terminal voltage Vout is supplied.
A common connecting node among the drains of the transistors 912, 915, and 921 is an output Vdf of the differential circuit 910.
The output stage 950 comprises a PMOS transistor 951 of which the drain is connected to an output terminal, a source is connected to a high-potential power supply terminal VDD, and the gate receives the output Vdf of the differential circuit 910, a constant-current source 952 connected between the output terminal and a low-potential source terminal VSS, and a phase compensating capacitor 953 connected between the gate of the PMOS transistor 951 and the output terminal.
The operational amplifier in FIG. 17 is a voltage follower circuit where a voltage equal to the input voltage Vin received at an input terminal 1 is outputted to an output terminal 2 as the output voltage Vout.
Next, an operation of the differential circuit 910 will be described. For simplicity of a description, a pair of transistors that constitute a differential pair or a current mirror circuit is assumed to have mutually identical transistor characteristics. Further, a description will be given, with a state where two differential input voltages Vin and Vout are equal defined as a reference state.
In the reference state where the Vin equals to the Vout, currents that flow through the pair of transistors of the PMOS differential pair (925, 926) are equal to each other, and each of the current is half a current of the constant-current source 927. The currents of the transistors 925 and 926 flow through the transistors 921 and 924, respectively, as mirror currents in the same magnitude due to the current mirror circuit (921, 922) and the current mirror circuit (923, 924). The currents that flow through the pair of transistors of the NMOS differential pair (915, 916) are also equal to each other, and each of the currents is half the current of the constant-current source 917. On the other hand, the currents that flow through the pair of the transistors of the current mirror circuit (912, 913) are also equal to each other. A sum of half the current of the constant-current source 917 and half the current of the constant-current source 927 flows through each of the transistors 912 and 913.
Since currents flowing through the pair of transistors of the differential pair are equal and currents flowing through the pair of the transistors of the current mirror circuit are equal in this manner, voltages at the terminals of the pair of transistors are also equal to each other. The output Vdf of the differential circuit (the output of the drain of the transistor 912) becomes stable around the drain voltage or the gate voltage of the transistor 913.
When the magnitude relation of the differential input voltages Vin and Vout becomes Vin>Vout, at the differential pair (915, 916), a gate-source voltage of the transistor 915 increases, and the gate-source voltage of the transistor 916 decreases, which functions to cause much current to flow through the transistor 915. For this reason, a discharging operation of the transistor 915 becomes strong, which functions to reduce the output Vdf of the differential circuit.
On the other hand, at the differential pair (925, 926), the gate-source voltage of the transistor 925 increases, and the gate-source voltage of the transistor 926 decreases, which functions to cause much current to flow through the transistor 925. Thus, the current of the transistor 921 through which its mirror current flows also increases. Accordingly, the discharging operation of the transistor 921 becomes strong, which also functions to reduce the output Vdf of the differential circuit.
When the magnitude relation of the differential input voltage Vin and Vout becomes Vin<Vout, at the differential pair (915, 916), the gate-source voltage of the transistor 916 increases, and the gate-source voltage of the transistor 915 decreases. Thus, the discharging operation of the transistor 915 becomes weak, which functions to increase the differential circuit output Vdf. On the other hand, at the differential pair (925, 926), the gate-source voltage of the transistor 926 increases, and the gate-source voltage of the transistor 925 decreases, which functions to limit the current of the transistor 925. The current of the transistor 921 through which its mirror current flows also decreases. For this reason, the discharging operation of the transistor 921 becomes weak, which also functions to increase the differential circuit output Vdf.
In this manner, in the differential circuit 910, when the Vin becomes larger than the Vout, the differential circuit output voltage Vdf is reduced. When the Vin becomes smaller than the Vout, the differential circuit output voltage Vdf increases. Accordingly, in the amplifier circuit in FIG. 17, when the Vin is larger than the Vout, the gate voltage of the PMOS transistor 951 in the output stage 950 is reduced, so that the output terminal 2 is charged at high speed. When the Vin is smaller than the Vout, the gate voltage of the PMOS transistor 951 is increased to be turned off. Then, the output terminal 2 is discharged through the constant-current source 952, and then becomes stable at a point where a drain current of the PMOS transistor 951 balances the current controlled by the constant-current source 952 and the Vin equals to the Vout.
A characteristic of the operational amplifier resides in the differential circuit 910. In the differential circuit 910, when the input voltage Vin is in a wide medium voltage range of a power supply voltage range (from a power supply VSS to a power supply VDD), the NMOS differential pair (915, 916) and the PMOS differential pair (925, 926) both operate, and through the differential circuit output Vdf, the gate of the transistor 951 in the output stage 950 is controlled, thereby allowing the operational amplifier to operate. Further, even if the input voltage Vin is around the power supply voltage and one of the differential pairs stops operation, the differential circuit output Vdf is normally output by the operation of the other differential pair. The operational amplifier can be thereby operated normally.
Assume that the input voltage Vin is around a low-potential power supply voltage VSS and becomes lower than a threshold voltage Vtn for the NMOS transistors 915 and 916. Then, the NMOS differential pair (915, 916) stops operation (to be in an off-state). However, the PMOS differential pair (925, 926), the NMOS current mirror circuits (921, 922 and 923, 924), and the PMOS current mirror circuit (912, 913) operate. Thus, through the differential circuit output Vdf, the output stage 950 can be operated normally.
On the other hand, when the input voltage Vin is around a high-potential power supply voltage VDD and the gate-source voltages of the PMOS transistors 925 and 926 become smaller than the absolute value for their threshold voltage Vtp, the PMOS differential pair (925, 926) stops operation (to be in the off-state). The NMOS current mirror circuits (921, 922 and 923, 924) also stop operation. The NMOS differential pair (915, 916) and the PMOS current mirror circuit (912, 913), however, operate. Thus, through the differential unit output Vdf, the output stage 950 can be operated normally. Accordingly, the operational amplifier in FIG. 17 can operate in a wide input and output range substantially equal to the power supply voltage range.
When the operational amplifier in FIG. 17 is employed in a driver circuit for a comparatively large capacitive load such as a liquid crystal display device, the charging operation on the output terminal 2 through the output stage 950 can be performed at high speed by the transistor 951. However, the discharging operation on the output terminal 2 is performed by the constant-current source 952. Thus, if the current of the constant-current source 952 is decreased, a discharging operation becomes slow and a driving speed becomes insufficient. If the current of the constant-current source 952 is increased, the discharging operation is performed at high speed. However, power consumption increases.
On contrast therewith, as operational amplifiers that enable the wide input and output ranges and achieve high-speed driving for both the charging and discharging operations on the output terminal, operational amplifiers in various publications (including JP Patent Kokai Publication JP-A-7-31351, JP Patent Kokai Publication JP-A-9-93055, and JP Patent Kokai Publication JP-P2000-252768) are known. FIG. 18 is a diagram showing a configuration of the operational amplifier listed as a typical example in JP Patent Kokai Publication JP-P2000-252768 (refer to FIG. 10 in this publication). Like the operational amplifier in FIG. 17, the operational amplifier in FIG. 18 is of a voltage follower structure for outputting a voltage equal to the input voltage Vin, as the output voltage Vout.
Referring to FIG. 18, this operational amplifier comprises a differential circuit 910, a connection stage 930, and an output stage 940. The differential circuit 910 has the same configuration as the differential circuit 910 in FIG. 17. Reference numerals that are the same as those in FIG. 17 are assigned to respective components in FIG. 18.
The connection stage 930 comprises a PMOS transistor 931, a constant-current source 934, a PMOS transistor 932, a PMOS transistor 933, and a constant-current source 935. The source of the PMOS transistor 931 is connected to a high-potential power supply terminal VDD, and the gate of the PMOS transistor 931 receives the differential unit output Vdf. The constant-current source 934 is connected between the drain of the PMOS transistor 931 and a low-potential power supply terminal VSS. The source of the PMOS transistor 932 is connected to a high-potential terminal VDD and the gate and the drain of the PMOS transistor 932 are connected to connection points between the drain of the PMOS transistor 931 and the constant-current source 934. The source of the PMOS transistor 933 is connected to a high-potential power supply terminal VDD and the gate of the PMOS transistor 933 is connected to a connection point between the drain of the PMOS transistor 931 and the constant-current source 934. The constant-current source 935 is connected between the drain of the PMOS transistor 933 and a low-potential power supply terminal VSS. A connection point between the drain of the PMOS transistor 933 and the constant-current source 935, is an output node of the connection stage 930.
The output stage 940 comprises a PMOS transistor 941, a PMOS transistor 942, and a phase compensating capacitor 943. The drain of the PMOS transistor 941 is connected to the output terminal 2, the source of the PMOS transistor 941 is connected to a high-potential terminal VDD, and the gate of the PMOS transistor 941 receives the differential unit output Vdf. The drain of the PMOS transistor 942 is connected to the output terminal 2, the source of the PMOS transistor 942 is connected to a low-potential power supply terminal VSS, and the gate of the PMOS transistor 942 receives the output of the connection stage 930. The phase compensating capacitor 943 is connected between the gate of the PMOS transistor 941 and the output terminal.
An operation of the differential circuit 910 in FIG. 18 is to allow outputting of the differential unit output Vdf over a wide input range substantially equal to the power supply voltage range, as in the case in FIG. 17.
The PMOS transistor 941 and the phase compensating capacitor 943 of the output stage 940 in FIG. 18 also have the same configurations as the PMOS transistor 951 and the phase compensating capacitor 953 of the output stage 950 in FIG. 17.
The operational amplifier in FIG. 18 is characterized in that the constant-current source 952 of the output stage 950 in the operational amplifier in FIG. 17 is replaced with the NMOS transistor 942, and the connection stage 930 for controlling the gate of the NMOS transistor 942 according to a change in the differential unit output Vdf is provided. Operations of the connection stage 930 and the output stage 940 will be described below.
The PMOS transistor 931 in the connection stage 930 receives the output Vdf of the differential stage, and performs the same operation as the PMOS transistor 941 of the output stage 940.
In other words, when the input voltage Vin becomes larger than the output voltage Vout, the voltage Vdf decreases from its stable state, so that the charging operation of the PMOS transistor 941 is produced to pull up the output voltage Vout. Since the PMOS transistor 931 also increases its drain voltage at this point, the PMOS transistor 933 is turned off, and the output of the connection stage 930 is reduced through the constant-current source 935. Accordingly, when the PMOS transistor 941 operates to increase the output voltage Vout, the NMOS transistor 942 is turned off.
On the other hand, when the Vin becomes smaller than the Vout, the voltage Vdf increases from its stable state, and the PMOS transistor 941 is turned off. At this point, the PMOS transistor 931 is also turned off, and its drain voltage is reduced through the constant-current source 934. Thus, the PMOS transistor 933 increases its drain voltage, thereby increasing the output voltage of the connection stage 930 and then turning on the NMOS transistor 942. Accordingly, when the PMOS transistor 941 is turned off, the discharging operation of the NMOS transistor 942 is produced to reduce the output voltage Vout at high speed.
Since the transistors 941 and 942 of the output stage 940 in the operational amplifier in FIG. 18 charges and discharges the output terminal 2, respectively, according to the output Vdf of the differential circuit 910, the charging and discharging operations can be performed speedily for driving the capacitive load as well.
However, the connection stage 930 in the operational amplifier in FIG. 18 quickly controls the discharging operation of the NMOS transistor 942, the connection stage 930 must quickly respond to a change in the voltage Vdf.
Accordingly, currents of the constant-current sources 934 and 935 for the connection stage 930 must be large to a certain extent, thereby causing a problem that the power consumption of the operational amplifier will increase.
Specifically, when the current of the constant-current source 934 has been reduced to a very low level, for example, a change in the gate voltage of the transistor 933 from the stable state to a low level becomes slower. Thus, a change in the gate voltage of the transistor 942 from the stable state to a high level is also delayed, so that a prompt discharging operation on the output terminal 2 cannot be performed.
On the other hand, when the current of the constant-current source 935 has been reduced to a very low level, a change in the gate voltage of the transistor 942 to the low level is delayed. Thus, even if the operation of the output stage 940 has been switched from the discharging operation to the charging operation, the transistor 942 is not quickly turned off. Thus, a short circuit current (through-current) is generated between the transistors 941 and 942.
Incidentally, a configuration of the connection stage 930, which is different from the one in FIG. 18 is also proposed in JP Patent Publication JP-P2000-252768. In either case, the currents of the constant-current sources constituting the connection stage must be large to a certain extent, so that there is the problem that the power consumption of the operational amplifier increases.